1. Field of the Invention
The invention relates in general to a data transmission technique, and more particularly, to a receiver in a physical layer of a Mobile Industry Processor Interface (MIPI-PHY).
2. Description of the Related Art
The Mobile Industry Processor Interface (MIPI) is an increasingly popular communication software/hardware interface standard in recent years, and is prevalent in products such as mobile electronic devices, digital cameras, display devices, portable tablets and laptop computers. In MIPI specifications, a physical layer serial interface commonly referred to as D-PHY provides a high-speed serial interface solution for communications between various components in an electronic device. The D-PHY solution is capable of expanding a bandwidth of a transmission interface through a low-power consumption approach.
For data transmission, the MIPI D-PHY specification defines two modes—a high-speed mode and a low-speed mode. In practice, a high-speed data receiving circuit and a low-power data receiving circuit at an MIPI D-PHY receiver share a pair of differential lines to receive messages from an MIPI transmitter. FIG. 1 shows a timing diagram of signals of the pair of differential transmission lines transmitting from a low-power mode to a high-speed mode. In FIG. 1, DP represents a positive end of the differential transmission lines, and the DN represents a negative end of the differential transmission lines. In the low-power mode (e.g., a period T0), both of the signals DP and DN are at a high-voltage level (1.2V). Before the MIPI transmitter is to exit the low-power mode and enter the high-speed mode to start transmitting data to the receiver, the signal DP is first reduced to a low-voltage level in a period (T1) and the signal DN is also reduced to a low-voltage level in a following period (T2). In a period T3, the transmitter needs to send high-speed differential signals 0 via the pair of differential transmission lines such that the signal DN is greater than the signal DP by 200 mV. In a period T4, the transmitter sends a synchronization signal for the reference of the receiver. After the period T4 ends, the transmitter starts transmitting real data contents.
According to MIPI D-PHY specifications, the receiver is required to enter the high-speed mode in period T2, i.e., a high-speed data receiving circuit at the receiver needs to starts operating. For the high-speed data receiving circuit, the signals DP and DN having a same voltage potential in the period T2 are invalid and unrecognizable signals. Also defined by the MIPI specifications, the receiver is required to ignore and mask the data received in the period T2. The period T3 may be regarded as a buffer zone of the masking period. More specifically, the receiver needs to mask at least the received data of the entire period T2, with a masking range covering a part of all of the period T3 but not the synchronization signal in the period T4.
A length of the above masking period has a lower limit of 85 ns+6*UI and an upper limit of 145 ns+10*UI, where ns represents nanoseconds, and UI represents a period of a clock signal adopted by the high-speed mode. In practice, a frequency of the clock signal changes with different settings, and a range of UI is between 1 ns and 12.5 ns. In order to correctly determine the length of the masking period, the MIPI receiver has to learn the value of UI. In current methods, the UI information is usually transmitted through hand-shaking between the transmitter and the receiver by means of software. However, in accordance with the above approach, a considerable amount of software resources are consumed, and unexpected situations, e.g., values incompliant with MIPI D-PHY specifications (e.g., when the UI length adopted at the transmitter exceeds 12 ns), usually cannot be handled.